1. Field of the Invention
The present invention generally relates to electronic clock circuits, and more particularly to an electronic clock for a microprocessor, that uses a phase-lock loop (PLL) circuit having an improved charge pump which compensates for common-mode voltages at the differential inputs of a voltage-controlled oscillator.
2. Description of the Related Art
Electronic circuits that provide clock signals are used in a wide assortment of devices, and particularly in computer systems. Microprocessors and other computer components, such as random access memory (RAM), device controllers and adapters, use clock signals to synchronize various high-speed operations. These computer clock circuits often use a phase-lock loop (PLL) circuit to synchronize (de-skew) an internal logic control clock with respect to an external system clock.
A typical prior art PLL circuit 1 is shown in FIG. 1 and includes a phase/frequency detector (PFD) 2, a charge pump 3, a low-pass filter 4, and a voltage-controlled oscillator (VCO) 5. Phase/frequency detector 2 compares two input signals, a reference signal f.sub.ref (from the external system clock) and a feedback signal f.sub.fb, and generates phase error signals that are a measure of the phase difference between f.sub.ref and f.sub.fb. The phase error signals ("UP" and "DOWN") from detector 2 are used to generate control signals by charge pump 3 which are filtered by low-pass filter 4 and fed into the control input of voltage-controlled oscillator 5. Voltage-controlled oscillator 5 generates a periodic signal with a frequency which is controlled by the filtered phase error signal. The output of voltage-controlled oscillator 5 is coupled to the input f.sub.fb of phase/frequency detector 2 directly or indirectly through other circuit elements such as dividers 6, buffers (not shown) or clock distribution networks (not shown), thereby forming a feedback loop. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the filtered phase error signal causes the frequency of voltage-controlled oscillator 5 to shift (upwards or downwards) toward the frequency of the reference signal, until voltage-controlled oscillator 5 finally locks onto the frequency of the reference; following frequency acquisition, phase acquisition is achieved in a similar manner. The output of voltage-controlled oscillator 5 is then used as the synchronized signal (for internal logic control). In cases where the incoming data is a self-clocking bit stream, the comparator system is used to extract the clock information from the data stream itself.
PLL's for microprocessors must exhibit high tolerance to electrical noise generated by the large number of rapidly switching logic circuits that are fabricated on the same die (silicon substrate or microchip). Differential circuits (rather than single-ended circuits) are accordingly preferred for these applications, but at present they are generally in use for only selected portions of the PLL, such as the voltage-controlled oscillator signal path (but not the control path of the voltage-controlled oscillator). See "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607 (November 1992), and "A Wide-Bandwidth Low-Voltage PLL for PowerPC.TM. Microprocessors" IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 383-391 (April 1995).
One problem that can arise with differential circuits in a PLL circuit relates to common-mode voltage. In a differential circuit, a value is based on the relative voltages of two signals, i.e., their difference, and not their absolute values. A common-mode voltage is a voltage that is applied equally to both signals, whereby the absolute values of the voltages are higher, although the difference between the voltages remains constant. A circuit element with differential inputs may be designed with an n-type field-effect transistor (nfet) source-coupled pair at the input, or a p-type field-effect transistor (pfet) source-coupled pair at the input. These transistors are sensitive to common-mode voltages that arise from the signal source, such as those resulting from excessive noise, leakage currents, and nfet or pfet operating characteristics. If the common-mode of the signal from the filter moves in such a way that the input stage begins to shut off (e.g., a high common-mode voltage for a pfet source-coupled pair), then the stability of the circuit can deteriorates dramatically and eventually fail to operate. This phenomenon is particularly troublesome with high-speed clock circuits, e.g., those with speeds greater than a few hundred megahertz.
One approach to handling such high common-mode voltages in a voltage-controlled oscillator would be to provide more sophisticated input stages. The resulting bandwidth reduction on the control input would, however, render such a voltage-controlled oscillator practically useless due to the loss of the required high frequency signal caused by the zero frequency in the transfer function. It would, therefore, be desirable and advantageous to devise an improved PLL clocking circuit having a differential component, such as a voltage-controlled oscillator, in which common-mode voltages of the inputs are controlled to alleviate the foregoing problems.